Senior HSIO Bench Test Engineer
Qualcomm
At a glance
AI generatedThe Post Silicon Engineering group at Qualcomm seeks a junior to mid-level Test Methodology Engineer to develop and execute test solutions for complex SOCs. This role involves defining and implementing characterization plans for high-speed interfaces like PCIe, USB3, UFS, and LP-DDR, ensuring compliance with electrical standards and optimizing design parameters. The engineer will collaborate closely with IC Design, Systems Engineering, and Customer Engineering teams to debug issues in silicon bring-up and validate performance across various conditions. Key skills include knowledge of VLSI technologies, high-speed test methodologies, and hands-on experience with lab equipment such as oscilloscopes and J-BERTs. Familiarity with Python for test automation and board design concepts is beneficial. The ideal candidate will possess strong problem-solving abilities and work effectively in a fast-paced environment.
Skills
What you'll do
What we're looking for
Market check
This $94,200–$141,200 range sits above 12% of similar postings on FindRole.
Peer median band
$124,127–$198,000
Median floor and ceiling across peers.
Typical midpoint (25–75%)
$134,625–$190,500
Middle half of comparable postings.
Based on 239 comparable postings.
* 240 is the maximum number of comparable postings sampled.
Employer
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has 569 open roles on FindRole.
Listed pay typically runs $148,300–$224,400 across 536 roles with salary data.
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