Careers
Quick summary
- Work type
- On-site
- Location
- San Diego, CA
- Posted
- 56 days ago
- Nearby
- 99+ roles within 25 mi
Market check
Salary context
How this pay compares to similar roles
This listing doesn't post a salary. Most similar roles pay $152,150–$208,800.
Based on 239 similar postings.
Employer
About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has 745 open roles on FindRole.
Listed pay typically runs $154,000–$231,000 across 423 roles with salary data.
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At a glance
TL;DR · Careers
The ASICS Design Verification Engineer role involves comprehensive pre-silicon test planning for digital power IP, including the development of advanced verification methodologies such as SystemVerilog-UVM and formal verification techniques. This position requires extensive experience in ASIC design and verification tools, RTL languages like SystemVerilog or Verilog, and scripting automation with Perl or Python. The ideal candidate will also have a strong background in computer architecture fundamentals and object-oriented programming concepts, along with expertise in developing block-level testbench environments using UVM. The team focuses on the entire verification lifecycle from concept to post-silicon support, emphasizing power-aware UPF verification flow and methodology development to enhance verification efficiency.
Skills
What you'll do
- Develop comprehensive pre-silicon test plans for digital power IP.
- Create and maintain advanced verification methodologies using SystemVerilog-UVM.
- Design coverage models to ensure thorough testing of digital power IPs.
- Develop assertion models and perform formal verification on designs.
- Implement automation scripts to enhance verification process efficiency.
What we're looking for
- Bachelor's degree in Engineering, Science, or a related field
- 2+ years of ASIC design and verification tools experience
- Master’s degree preferred in Computer Science, Electrical Engineer, etc.
- 6+ years developing block-level testbench environment using SystemVerilog
- Experience with UVM/OVM verification methodologies and formal verification
- Scripting/automation skills using Perl or Python required
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