Careers
Quick summary
- Work type
- On-site
- Location
- San Diego, CA
- Posted
- 52 days ago
- Nearby
- 99+ roles within 25 mi
Market check
Salary context
How this pay compares to similar roles
This listing doesn't post a salary. Most similar roles pay $152,075–$208,800.
Based on 239 similar postings.
Employer
About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has 660 open roles on FindRole.
Listed pay typically runs $154,000–$231,000 across 429 roles with salary data.
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At a glance
TL;DR · Careers
As a Timing Engineer at Qualcomm, you will join the Physical Design team as a mid-level professional, focusing on timing analysis for SOC products in advanced process technologies like 5nm and 4nm. Your daily responsibilities include collaborating with physical design teams to ensure timing closure, developing and validating flow scripts/tools, conducting Spice simulations for PVT corners validation, and facilitating STA methodology using PT-SI and Tempus. You will also contribute to the timing sign-off of complex SOC projects and improve overall timing convergence processes across the company. Key skills required include expertise in DC/DCT/DCG/Genus/Oasis, ICC2/Fusion/Innovus/Aprisa, RedHawk/SeaHawk/Voltus, and proficiency in Python, Perl, TCL, Unix shell, and C/C++. Knowledge of ML modeling is beneficial as you work on innovative solutions for timing analysis in mobile, compute, automotive, and IoT markets.
Skills
What you'll do
- Conduct timing analysis for SOC products at block/IP-level and system-level in 5nm, 4nm processes.
- Validate Spice simulations for PVT corners and ensure STA vs spice correlation using PT/PT-SI and Tempus.
- Develop and validate flow scripts/tools with CAD teams for timing closure and methodology improvement.
- Facilitate STA methodology for Qualcomm projects, contributing to timing sign-off of complex SOC’s.
- Enhance timing convergence process across the company to improve design PPA and yield.
What we're looking for
- Extensive experience in timing analysis for SOC products at block/IP-level and system-level in advanced process technologies (5nm, 4nm).
- Proficient in Spice simulations and STA tools validation across various PVT corners using PT/PT-SI, Tempus.
- Expertise in facilitating and driving STA methodology for complex SOC projects, including timing sign-off specifications.
- Strong understanding of digital flow from RTL to GDS, with experience in multiple EDA tools (DC/DCT/ICC2/Fusion).
- Excellent programming skills in Python, Perl, TCL, Unix shell, C/C++ for automation and scripting.
- Knowledge of ML modeling techniques is beneficial for enhancing timing convergence processes.
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