Careers

Qualcomm

Quick summary

Work type
On-site
Location
San Diego, CASanta Clara, CA
Posted
52 days ago

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Salary context

How this pay compares to similar roles

Similar $180k
$118k most similar roles pay here $247k

This listing doesn't post a salary. Most similar roles pay $152,075–$208,800.

Based on 239 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 660 open roles on FindRole.

Listed pay typically runs $154,000–$231,000 across 429 roles with salary data.

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At a glance

TL;DR · Careers

As an ASIC Methodology Engineer at Qualcomm’s DTECH team within the Global SOC organization, you will collaborate with core and SOC teams to develop a cutting-edge design analytics platform that significantly impacts power, performance, area, and quality of Qualcomm’s products. Your daily responsibilities include enabling state-of-the-art methodologies for static timing analysis (STA) using tools like PrimeTime and Tempus, and you will need strong programming skills in Python along with hands-on experience in ASIC/VLSI design flows. Additionally, familiarity with GenAI models and their application in real-world solutions is preferred, as well as experience with version control systems such as Perforce or Git and place & route tools. This role requires a problem-solving mindset and the ability to develop scalable platforms for large-scale design automation challenges.

What you'll do

  • Develop state-of-the-art design analytics platforms for power, performance, area optimization.
  • Enable SOC teams with advanced static timing analysis using tools like PrimeTime and Tempus.
  • Collaborate on low-power architecture methodologies and IP development within the DTECH team.
  • Implement scalable software architectures to enhance internal EDA tool capabilities.
  • Utilize Python programming skills to automate design flows and improve efficiency.

What we're looking for

  • M.S/Ph.D. in Electrical Engineering or Computer Science with 1-2 years of relevant experience in ASIC/VLSI design tools and flows.
  • Strong proficiency in Python programming for engineering applications.
  • Extensive hands-on experience with static timing analysis (STA) tools like PrimeTime and Tempus.
  • Proven ability to solve complex problems using analytical skills.
  • Familiarity with version control systems such as Perforce or Git.

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