Careers

Qualcomm

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$195,200–$292,800 / yr
Posted
52 days ago

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $180k
This role $244k
$111k most similar roles pay here $312k

This role pays more than 93% of similar roles. Most pay $152,075–$208,800 — the shaded band above. At the midpoint, this role pays about $244k versus about $180k for comparable roles.

Based on 239 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 660 open roles on FindRole.

Listed pay typically runs $154,000–$231,000 across 429 roles with salary data.

Most-posted roles

View all roles at Qualcomm

At a glance

TL;DR · Careers

The Senior Staff Design Verification Engineer role involves leading the team to enhance engineering efficiency and product quality by developing comprehensive test plans and conducting functional verification at various levels including IP, sub-system, SoC, and system/architecture for both wireless and wired technologies using SystemVerilog in OVM or UVM environments. Daily tasks include collaborating with architects, ASIC designers, and software engineers on mobile handset and consumer electronic applications to write feature-based test plans, debug failures, run regressions, and close test plan targets while actively participating in design reviews and project meetings. The ideal candidate should have expertise in SystemVerilog, OVM/UVM verification methodologies, and experience with physical and MAC layer verification, along with a strong background in electrical engineering, computer science, or related fields, either at the master's level with seven years of experience or bachelor’s level with nine years of progressive experience.

What you'll do

  • Develops test plans and conducts functional verification at IP, sub-system, SoC levels.
  • Implements SystemVerilog in OVM/UVM environments for hardware verification.
  • Leads Physical/Mac Layer verification for wireless and wired technologies.
  • Collaborates with Architects, ASIC designers, and Software Engineers on SoCs.
  • Writes feature-based test plans, debugs failures, runs regressions, closes targets.

What we're looking for

  • 7+ years of relevant engineering experience with SystemVerilog and UVM/OVM environments.
  • Strong background in hardware verification at IP, sub-system, SoC, and system levels.
  • Experience leading teams to enhance engineering efficiency and product quality.
  • Proficient in developing test plans, debugging failures, and running regressions.
  • Collaborative work with architects, ASIC designers, and software engineers on complex projects.
  • Expertise in physical and MAC layer verification for mobile handset and consumer electronics.

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