Careers
Quick summary
- Work type
- On-site
- Location
- San Diego, CA
- Posted
- 3 days ago
- Closes
- Nov 30, 2026
- Nearby
- 99+ roles within 25 mi
Market check
Salary context
How this pay compares to similar roles
This listing doesn't post a salary. Most similar roles pay $152,037–$208,800.
Based on 238 similar postings.
Employer
About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has 558 open roles on FindRole.
Listed pay typically runs $154,000–$231,000 across 401 roles with salary data.
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At a glance
TL;DR · Careers
The Memory Subsystem Performance Architect at Qualcomm Technologies will lead the performance modeling and optimization of high-bandwidth memory subsystems for next-generation SoCs, working closely with architecture, design, and software teams from concept to post-silicon validation. This role involves developing C++/SystemC models to analyze HBM-based systems, identifying bottlenecks across memory, interconnect, caches, and compute, and collaborating with cross-functional teams to influence design decisions. The ideal candidate has 3+ years of experience in performance modeling or system architecture, strong proficiency in C++, and knowledge of memory hierarchies and DRAM systems. Preferred qualifications include hands-on experience with HBM2/3 architectures, AI/ML SoCs, and post-silicon analysis, making this a critical role for advancing cutting-edge semiconductor technology.
Skills
What you'll do
- Develop and maintain C++ / SystemC performance models for HBM-based memory subsystems.
- Define and execute experiments to evaluate HBM architecture features and system-level trade-offs.
- Identify performance bottlenecks across HBM, interconnect, caches, and compute.
- Influence design decisions by collaborating with cross-functional teams on SoCs.
- Research industry trends and innovations in HBM and advanced packaging.
What we're looking for
- 3+ years of experience in performance modeling or memory/system architecture.
- Proficient in C++ and experienced with SystemC/TLM modeling.
- Solid understanding of memory hierarchies and DRAM systems.
- Hands-on experience with HBM2/HBM2E/HBM3 architectures preferred.
- Experience with AI/ML, GPU, or HPC-class SoCs beneficial.
- Familiarity with post-silicon performance analysis and silicon correlation.
- Ability to translate performance data into clear architectural recommendations.
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