Camera Design Engineer

Qualcomm

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $148,300–$222,500 / yr
Posted: 112 days ago
Closes: Aug 23, 2026
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $197k

This role $185k

$136k most similar roles pay here $253k

This role pays less than 57% of similar roles. Most pay $166,925–$226,600 — the shaded band above. At the midpoint, this role pays about $185k versus about $197k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 745 open roles on FindRole.

Listed pay typically runs $154,000–$231,000 across 423 roles with salary data.

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At a glance

TL;DR · Camera Design Engineer

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Qualcomm Technologies is seeking an ASIC Design Engineer to join its Multimedia Camera HW team at various seniority levels from entry-level to mid-career professionals with up to six years of experience. The role involves collaborating with hardware and system architects to design advanced image and video processing blocks, owning the delivery of core level IP through RTL design, and conducting rigorous checks such as synthesis, low power analysis, and cross-clock domain verification. Engineers will also develop test plans and reference models in conjunction with verification teams, implement tests at both module and core levels, and maintain detailed documentation throughout the development cycle. Ideal candidates should possess expertise in Verilog or VHDL RTL design, bus protocols like AHB and AXI, and have experience with image, video, graphics, multimedia processing, and DSP technologies. Familiarity with RTL sanity tools for Design Rule Checking (DRC), Clock Domain Crossing checks, synthesis, timing analysis, and low power checks is essential, while knowledge of System Verilog or C++, ASIC implementation in Image Processing Camera IP, and scripting languages like TCL/Perl/Python/shell-scripting are highly desirable.

Skills

Verilog VHDL RTL design Design Verification AHB AXI Image Processing Video Processing Graphics Processing Multimedia Processing DSP RTL sanity tools Design Rule Checking Clock Domain Crossing checks Synthesis Timing analysis Low power checks System Verilog System C TCL Perl Python shell-scripting

What you'll do

Design and micro-architect HW for Multimedia and Camera Image Signal Processing algorithms.
Own and deliver core level IP through RTL design and synthesis.
Perform DRCs, low power checks, and CDC checks to ensure QoR.
Evaluate performance, area, power, and system cost tradeoffs throughout development.
Develop test plans and reference bus-functional models with verification engineers.

What we're looking for

3+ years of industry experience in Verilog or VHDL RTL design.
Experience with image, video, graphics, multimedia processing, or DSP.
Proficiency in design verification and bus protocols like AHB, AXI.
Ability to perform design rule checks, low power checks, and cross-clock-domain checks.
Strong communication and planning skills for daily cross-functional interaction.
Knowledge of RTL sanity tools for synthesis, timing analysis, and low power checks.

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