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Wireless Design Engineer

Apple Inc

Sunnyvale, CA 29 days ago $181,100–$318,400
Actively hiring Verified listing Above market
RTL SystemVerilog Verilog Python Perl Shell CDC RDC STA Lint ASIC MAC Bluetooth WLAN Zigbee AXI APB AHB Memory systems Power management Encryption/decryption engines High-speed data path Control units
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Wireless SoC Design Engineer

Apple Inc

Sunnyvale, CA 38 days ago $126,800–$220,900
Actively hiring Verified listing Competitive pay
SystemVerilog RTL Lint CDC RDC Synthesis STA Memory_subsystems Bus_interfaces CPU_integration DMA_engines Compression Security_IP_design PCIE QSPI UART SPMI Cross_clock_domain_design ASIC_low_power_design Multiple_supply_domains Dynamic_power_scaling Power_analysis DFT Scan_insertion Memory_BIST
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