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Senior ASIC Timing Engineer

Nvidia

Santa Clara, CA 3 days ago $136,000–$218,500
Actively hiring Posted this week Verified listing Competitive pay
Static Timing Analysis Timing Constraints Generation ECOs Physical Design Optimization Synthesis Placement Routing Logic Restructuring STA Tools Deep Sub-Micron Process Nodes GPU STA CPU STA LPD STA SOC STA Logic Synthesis Equivalence Checking DFT Logic AMS Designs Methodology Development Flow Development Automation
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