As an innovative Timing Methodology Engineer joining NVIDIA’s cutting-edge team, you will drive multi-physics sign-off strategies for leading GPUs and SoCs, optimizing performance, yield, and reliability through advanced modeling, analysis, and automation. Your daily tasks include improving and validating flows for Prime-Time, Prime-Shield, and Tempus STA QoR metrics, developing custom validation flows for ETM models, and creating sophisticated sign-off methodologies to address deep submicron physical effects such as aging and thermal impact. You will collaborate with technology leads, VLSI physical design teams, and timing engineers to define and deploy cutting-edge strategies that enhance silicon performance across various product lines, from consumer graphics to autonomous vehicles. Essential skills include a Master’s or PhD in Electrical or Computer Engineering, Python programming, experience with automated regression tests, knowledge of VLSI concepts, and understanding of circuit design fundamentals. Additional proficiency in Perl and TCL is beneficial, as is the ability to work effectively across multiple teams simultaneously.
Skills
Python
Perl
TCL
VLSI
STA
Prime-Time
Prime-Shield
Tempus
ETM
CMOS
Clocking
Synchronous_circuits
Jitter
IR_drop
Crosstalk
Spice_analysis
CI/CD
What you'll do
Improve and validate flows for Prime-Time, Prime-Shield, and Tempus STA QoR metrics for high-speed designs.
Develop custom flows to validate ETM models for standard cells and custom IPs.
Create methodologies to model deep submicron physical effects like aging, self-heating, thermal impact, and IR drop.
Define and deploy advanced strategies for signing off timing in design for world-class silicon performance.
Develop tools and methodologies to enhance design predictability and reliability beyond industry standards.
What we're looking for
Master's or PhD in Electrical or Computer Engineering required.
Proven ability to solve complex VLSI problems.
Expertise in Python programming and scripting languages (Perl, TCL).
Experience developing automated regression tests for validation.
Deep understanding of CMOS design, clocking, and synchronous circuit timing.
Knowledge of mathematics/physics fundamentals in circuit design.
Market check
Salary context
This
$116,000–$189,750
range sits above
49%
of similar postings on FindRole.
Peer median band
$117,000–$195,500
Median floor and ceiling across peers.
Typical midpoint (25–75%)
$135,000–$175,937
Middle half of comparable postings.
Based on 240 comparable postings.*
* 240 is the maximum number of comparable postings sampled.
Employer
About Nvidia
Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing
Nvidia currently has
801 open roles
on FindRole.
Listed pay typically runs
$184,000–$287,500
across 797 roles with salary data.
Us, Ca, Santa Clara, US10 days ago
$168,000–$264,500
Perl
Python
Tcl
Make
Synopsys DC
Synopsys FC
Cadence Genus
Cadence Innovus
VLSI
EDA
Logic Design
Physical Design
Place and Route
Synthesis
Formal Equivalence Checking
CI/CD
Us, Or, Hillsboro, US18 days ago
$124,000–$195,500
CUDA
Python
C++
GPU
Distributed Systems
AI
Machine Learning
Deep Learning
Algorithm Development
Memory Management
Cache Compression
Workload Balancing
Parallel Programming
Computational Geometry
Diffractive Optics
Us, Ca, Santa Clara, US31 days ago
$100,000–$166,750
Linux
Windows
x86
ARM
BMC
PCIe
GPU
High Performance Computing
AI
Oscilloscopes
Logic Analyzers
Multi-meters
Linux Environments
Enterprise System Architecture
CPU Architecture
Technical Documentation
Product Specifications
Hardware Design Guides
Application Notes