Senior Director, Architecture Research Lab

Samsung Semiconductor

Quick summary

Work type: On-site
Location: San Jose, CA
Salary: $246,000–$430,000 / yr
Posted: today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $217k

This role $338k

$138k most similar roles pay here $461k

This role pays more than 99% of similar roles. Most pay $178,781–$256,000 — the shaded band above. At the midpoint, this role pays about $338k versus about $217k for comparable roles.

Based on 240 similar postings.

Employer

About Samsung Semiconductor

Samsung Semiconductor is the global semiconductor business unit of Samsung Electronics, designing and manufacturing memory chips, logic semiconductors, and foundry solutions for a broad range of applications.

Samsung Semiconductor currently has 54 open roles on FindRole.

Listed pay typically runs $163,000–$253,000 across 54 roles with salary data.

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View all roles at Samsung Semiconductor

At a glance

TL;DR · Senior Director, Architecture Research Lab

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As a Senior Director in the Architecture Research Lab, you will lead pioneering research on next-generation AI system architectures, focusing on co-designing high-performance processors and hardware platforms that integrate Samsung’s advanced memory technologies. Your daily responsibilities include defining system-level architectures to address capacity, bandwidth, and communication challenges for large-scale AI workloads such as language models and recommendation systems. You will build simulation frameworks, conduct design-space exploration, and guide micro-architecture research for RISC-V CPU cores, ensuring optimal performance through detailed specifications and workload analysis. Additionally, you will manage a multidisciplinary team, set technical roadmaps, and present strategic recommendations to senior leadership. The role requires expertise in system-level architecture, performance modeling, simulation tools like Python and C++, and experience with large-scale computing platforms.

Skills

Python C++ RISC-V ARM x86 TLM event-driven simulation performance modeling PPA analysis out-of-order CPUs CPU/accelerator architectures heterogeneous integration rack-scale AI systems simulation tools

What you'll do

Define system-level architectures to solve memory-capacity, bandwidth, and interconnect challenges for large AI workloads.
Build and maintain simulation frameworks for compute-memory-network performance at rack scale.
Conduct design-space exploration and quantitative trade-off studies to guide architecture decisions.
Architect high-performance RISC-V CPU cores as host processors for AI computing systems.
Lead a multidisciplinary research team, set technical roadmaps, and ensure delivery of impactful publications.

What we're looking for

Ph.D. in Computer Science, Electrical Engineering, or a related field.
10+ years of experience in system-level architecture research for AI workloads.
Expertise in performance modeling and event-driven simulation frameworks.
Deep knowledge of modern CPU/accelerator architectures (RISC-V, ARM, x86).
Proven ability to design rack-scale AI system architectures addressing memory constraints.
Experience in large-scale design-space exploration and PPA trade-off analysis.

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