| Microsoft Careers

Microsoft

Quick summary

Work type
On-site
Location
—
Salary
$142,800–$274,800 / yr
Posted
59 days ago

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $180k
This role $209k
$101k most similar roles pay here $293k

This role pays more than 95% of similar roles. Most pay $152,150–$207,350 — the shaded band above. At the midpoint, this role pays about $209k versus about $180k for comparable roles.

Based on 239 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 1580 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 1408 roles with salary data.

Most-posted roles

View all roles at Microsoft

At a glance

TL;DR · | Microsoft Careers

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The Principal Silicon DV Engineer role within the Silicon, Manufacturing and Packaging Engineering (SMPE) team at Microsoft involves defining and leading verification strategies, quality, and test plans for hardware manufacturing. This senior-level position requires managing multiple development activities across various product groups while developing system and silicon debug tools to support debugging efforts. Day-to-day responsibilities include creating and maintaining test benches using System Verilog Test Bench (SVTB), UVM, and Python scripts, as well as innovating verification methodologies and integrating generative AI solutions to enhance efficiency. The ideal candidate has extensive experience in pre-silicon SOC, chip-level, or subsystem verification and a strong background in electrical engineering, computer science, or related fields, with the ability to drive complex projects from inception to completion.

Skills

SystemVerilog UVM Python C Docker CI/CD AWS Kubernetes Terraform Prometheus Grafana Git Jenkins

What you'll do

  • Define and lead verification strategies and quality test plans for hardware manufacturing.
  • Develop and integrate DV test content and automation solutions for ATE platforms.
  • Manage multiple development activities across various product groups.
  • Innovate to enhance verification efficiency through methodologies or tools.
  • Apply generative AI solutions to improve verification processes.

What we're looking for

  • Doctorate in EE/CE/CS or related field with 5+ years of experience; Master's with 8+ years; Bachelor's with 12+ years.
  • At least 5 years of pre-silicon SOC, chip level, or sub-system verification experience.
  • Experience defining and leading verification strategies, quality, and test plans.
  • Proficiency in System Verilog Test Bench (SVTB), UVM, and creating/maintaining test benches.
  • Aptitude for writing scripts/software using industry-standard languages like Python.
  • Ability to innovate and improve verification efficiency through methodologies or tools.

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