| Microsoft Careers

Microsoft

Quick summary

Work type: On-site
Location: Redmond, WA
Salary: $142,800–$274,800 / yr
Posted: 54 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $181k

This role $209k

$101k most similar roles pay here $293k

This role pays more than 95% of similar roles. Most pay $155,000–$207,350 — the shaded band above. At the midpoint, this role pays about $209k versus about $181k for comparable roles.

Based on 238 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 1103 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 985 roles with salary data.

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At a glance

TL;DR · | Microsoft Careers

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Join our dynamic AISiE team as a Principal Physical Design Engineer, where you will lead the development of TFM (tool, flow, methodology) for physical design tasks at block, sub-chip, or full-chip levels, focusing on Place and Route (PnR), Static Timing Analysis (STA), Physical Verification (PV), Formal Equivalency Verification (FEV), Functional ECO, Clocking Construction, and IR-Drop/EM. Your day-to-day will involve improving physical design efficiency, implementing methodologies for sign-off in static timing and verification areas, conducting reviews to resolve issues, and guiding junior engineers. You should have expertise with Synopsys Fusion Compiler, Cadence Innovus, Siemens Calibre, TCL scripting, and Python, along with a strong background in semiconductor design principles and leading-edge tapeouts of complex ASICs. This role demands a Bachelor's or Master’s degree in Electrical/Computer Engineering and over 10 years of experience in physical design projects.

Skills

TCL Python Synopsys_Fusion_Compiler Cadence_Innovus Siemens_Calibre Synopsys_Primetime Formality VCLP Star-RC Static_Timing_Analysis Physical_Verification Formal_Equivalency_Verification Functional_ECO Clocking_Construction IR-Drop_EM Tapeout ASIC_Design Semiconductor_Design_Principles Foundry_Tech_Files_Rule_Decks

What you'll do

Lead the development of PnR convergence recipes for block and subsystem designs.
Improve physical design efficiency and performance through innovative methodologies.
Ensure sign-off of blocks and subsystems in static timing, verification, and low power areas.
Implement functional ECO with minimal impact on physical design integrity.
Design global clocking schemes at SOC and sub-chip levels to optimize performance.

What we're looking for

10+ years of experience in blocks level place and route for complex ASICs.
Expertise in physical design EDA tools like Synopsys Fusion Compiler, Cadence Innovus, and Siemens Calibre.
Proven track record of leading successful physical design projects and delivering high-quality semiconductor products.
Strong understanding of semiconductor design principles and methodologies.
Adequate scripting skills in TCL and Python for automation and optimization.
Effective communication and leadership abilities to drive cross-functional collaboration.
Good understanding of foundry tech files and rule decks.

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