| Microsoft Careers

Microsoft

Quick summary

Work type: On-site
Location: —
Salary: $102,100–$202,200 / yr
Posted: 16 days ago
Closes: Nov 16, 2026

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $180k

This role $152k

$86k most similar roles pay here $251k

This role pays less than 74% of similar roles. Most pay $152,150–$208,800 — the shaded band above. At the midpoint, this role pays about $152k versus about $180k for comparable roles.

Based on 239 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 728 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 664 roles with salary data.

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At a glance

TL;DR · | Microsoft Careers

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The Design Verification Engineer position at Microsoft’s Compute Silicon & Manufacturing Engineering team requires a mid-level professional to contribute to the development and validation of custom silicon components. This involves writing constrained random stimulus, scoreboards, checkers, and assertions to ensure design correctness, developing Verification IP (VIP) and UVM components for simulation environments, and defining functional coverage metrics. The role demands collaboration with cross-functional teams including Architecture, Design, Firmware/Software, Product Engineering, and Program Management to enhance pre-and-post-silicon testing comprehensiveness. Essential skills include experience in SystemVerilog, C/C++, Python or similar scripting languages, UVM/OVM methodologies, and a deep understanding of complex IP/blocks such as coherency, caches, fabrics, DDR controllers, PCIe, CXL, AXI/CHI protocol bridges. This role is integral to Microsoft’s cloud hardware manufacturing efforts, focusing on quality, delivery, scale, and sustainability at an enterprise level.

Skills

SystemVerilog C++ Python Ruby Perl UVM OVM SystemVerilog_Test_Bench(SVTB) Formal_Verification CI/CD Git JIRA Microsoft_Teams

What you'll do

Write constrained random stimulus, scoreboards, and checkers to verify design correctness.
Develop Verification IP (VIP) components to ensure home-grown designs are verified accurately.
Define and implement functional coverage to drive verification process efficiency.
Create Universal Verification Methodology (UVM) components for test code simulation interfaces.
Develop scripts for verification and validation infrastructure to enhance testing processes.

What we're looking for

Master's degree in Electrical/Computer Engineering, Computer Science or equivalent experience required.
2+ years of technical engineering experience with a focus on verification and validation.
3+ years of pre-silicon SOC/IP verification experience preferred.
Proficiency in SystemVerilog, C/C++, Python, Ruby, or Perl scripting languages.
Experience with UVM/OVM methodologies for testbench creation and stimulus generation.
Demonstrated expertise in complex IP/blocks such as caches, fabrics, DDR controllers, PCIe, etc.
Knowledge of full product cycle from definition to silicon validation.

| Microsoft Careers

Microsoft

US 46 days ago

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