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Memory Subsystem Performance Architect

Qualcomm

San Diego, CA 9 days ago $140,000–$210,000

Actively hiring Verified listing Below market

C++ SystemC HBM Memory_Hierarchies DRAM_Systems AI/ML GPU HPC Post_Silicon_Performance_Analysis SoC_Architecture TLM HBM2 HBM2E HBM3

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Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer

Qualcomm

San Diego, CA 27 days ago $140,000–$210,000

Actively hiring Below market

RTL Verilog SystemVerilog VHDL ASIC LPDDR HBM NoC CPU x86 ARM Cache Controller Memory Subsystem Digital Design Synthesis Timing Closure Physical Design Gate Level Simulation Power Analysis RTL Design Verification

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