Power Integrity Engineer

• Power delivery modeling, simulation, and characterization for die, interposer, package, board, and Voltage Regulator. • Close collaboration with multi-functional teams to design end-to-end power delivery systems for both current and future generations. • Definition of the PDN architecture and design solution space for the target system • Broad responsibility on all SoC droop related topics, including on-die inrush, off-die droop budget, PDN sign-off, noise coupling analysis, voltage guard band, active droop mitigation etc. Conduct end-to-end simulation studies including modeling of die/interposer/PKG/PCB/PMU, to meet stringent impedance and voltage droop spec. Provide implementation guidelines and feedbacks to silicon, package, system design and other cross-functional teams. Perform feasibility study for silicon floorplan, advanced droop mitigation schemes, voltage regulator modeling and tuning, system mockup design etc. Perform model to hardware correlation on component and product/system level. BS and 3+ years of relevant industry experience. M.S and or Ph.D. with academic background in Power/Signal Integrity, Analog Circuit Design or Electromagnetism. Proficiency in Python coding, AI/ML assisted automation experience. Experience in PI/SI methodology development, PDN modeling from system to die, and lab correlation/validation. Experience in design and analysis of product power supply solution. Understanding of power supply architecture covering voltage regulator technologies, PCB and package design trends and trade-offs, and chip supply design including low-power design methodologies. Deep understanding of Voltage Regulator design principles and electrical performance in the system environment. Good knowledge in 3D/2D EM simulation tools, electromagnetic and transmission line theory. Familiar with lab equipment including but not limited to VNA, real-time scope, spectrum analyzer. Ability to work and communicate efficiently in a multi-functional team.

For more details click Job Post.