Embedded Real Time Critical Control Firmware Engineer

Define the long-range technical strategy for constrained real-time firmware across cellular SoC generations. Drive system-level architectural decisions that span algorithm design, AI/ML integration, and hardware co-design. Serve as the primary technical authority for the organization on embedded firmware, setting direction that influences product roadmaps and silicon investments over multi-year horizons. Architect and drive the end-to-end technical strategy for algorithms including power gating, tracking loops, and physical layer procedures, setting design patterns adopted across the firmware organization. Define and champion the validation philosophy and methodology for the firmware organization, establishing frameworks and quality standards that scale across multiple programs and teams. Lead the pre-silicon emulation and virtual platform strategy in partnership with hardware teams; drive co-design decisions that reduce firmware bring-up risk across future SoC generations. Define the tooling and infrastructure roadmap for build, formal verification, and test; drive adoption of emerging methodologies (including AI-assisted verification) across the organization. Provide deep technical mentorship to senior and principal engineers; build engineering culture and raise the technical bar across the firmware community. Partner with silicon architecture, SoC design, and product teams to influence multi-generation hardware/software co-design decisions at the earliest planning stages. BS and a minimum of 18 years of relevant industry experience, with a demonstrable track record of technical leadership and broad organizational impact. Experience with design and implementation of bare metal control firmware which is highly optimized for cycles and memory. Deep understanding of the difference between design for a software platform and a highly constrained firmware environment. Demonstrated history of owning and delivering multi-generational firmware programs across the complete hardware/software lifecycle, from early silicon architecture through production. Recognized expertise in architecting complex, cross-functional system-level solutions that span firmware, hardware, and protocol layers; experience driving architectural decisions with organization-wide adoption. Fundamental facility with C and C++, compilers, build and source code control tools. Solid understanding of computer architecture with particular emphasis on the HW/SW interfaces of high-speed communication subsystems. Some mainstream OS application-level development and Python or Perl scripting experience. Strong foundation in Machine Learning and Deep Learning: Experience with ML algorithms and deep learning architectures (e.g., CNNs, RNNs, Transformers). Proven track record of applying ML/AI techniques to production firmware systems, not only as a productivity tool but as a core design principle for algorithm design and parameter estimation. Strategic use of generative AI to accelerate design, verification, and team productivity at an organizational scale. Theoretical understanding of the implementation of AI/ML Algorithms: In-depth knowledge of the mathematical foundations of various AI/ML algorithms and how to apply to parameter estimation algorithms. Understanding of HW architectures and programming models for how to target algorithms to AIML acceleration HW. Understanding of design for asymmetric multiprocessing solutions. Deep expertise in 5G and 4G 3GPP protocols with experience contributing to or tracking standards development; ability to translate standards evolution into firmware architecture strategy. Advanced understanding of wireless communications theory and system design, sufficient to engage with modem algorithm teams and make authoritative HW/SW co-design trade-offs. Extensive experience driving silicon prototyping and pre-silicon bring-up strategies across multiple SoC generations; recognized as an authority in pre-silicon firmware methodology. Deep, organization-shaping expertise with memory-constrained RTOS and concurrent programming, including architectural contributions to RTOS design or scheduling policy for constrained cellular firmware environments. History of growing and retaining senior technical talent; recognized as a mentor and multiplier within a large engineering organization.

For more details click Job Post.